The present invention relates to delay handling in modulator loops. More specifically, the present invention provides a filter in the modulator loop which compensates for delays introduced by, for example, a power switching stage or an output filter.
With pulse width modulation (PWM) and other modulation techniques, the delay introduced by switching and output filter stages must be effectively dealt with to alleviate the adverse effects such delays have on circuit stability. This is particularly true for modulators which have relatively high power switching stages because the delays can become very large with respect to the pulse repetition frequency of the loop. A traditional solution to the problem of delay handling will be described with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram of a typical modulator loop 100. The logic output of modulator 102 drives an inverting power stage 104 the output of which is filtered by output filter 106. A feedback resistor 108 and attenuation resistor 112 are provided for the purpose of introducing negative feedback from the output of the loop to modulator 102. FIG. 2 shows two waveforms 202 and 204 from the modulator loop of FIG. 1 without delay compensation. As shown, due to the delay introduced by the switching and filter stages, the positive swing of waveform 204 (i.e., the output filter 106) is nearly in phase with the positive swing of waveform 202 (i.e., the logic output of modulator 102).
Thus, where the original design of the loop contemplates negative feedback, the delay converts it to positive feedback and therefore loop instability (not shown) results. For this reason, a filter capacitor 110 is provided in parallel with feedback resistor 108 for delay compensation. Capacitor 110 produces a zero in the feedback loop, effectively bypassing the attenuation caused by resistors 108 and 112 for high frequencies.
Unfortunately, because this type of delay compensation is performed after the delay has been introduced into the loop, it is difficult to correct all of the delay's negative consequences with regard to loop stability. In fact, this type of compensation technique has had only limited success and, as a result, has limited the delay tolerance and the overall performance of today's modulators. One solution is to use feedback signals directly from the logic output of the modulator, i.e., before the delay is introduced, in combination with the output of the power stage and/or the output filter. Unfortunately, while the output of the modulator (202) and the filter output (204) have similar characteristics there are significant differences in content in the modulator loop's frequency range of interest due to the non-ideal nature of the power stage as discussed in U.S. patent application Ser. No. 08/898,544 for METHOD AND APPARATUS FOR PERFORMANCE IMPROVEMENT BY QUALIFYING PULSES IN AN OVERSAMPLED, NOISE-SHAPING SIGNAL PROCESSOR filed on Jul. 22, 1997, the entire specification of which is incorporated herein by reference. This makes it very difficult to achieve high fidelity operation while feeding these signals back.
In view of the foregoing, it is desirable to provide an improved technique for compensating for delays in modulator loops such that greater delays may be tolerated without adversely affecting loop stability.